1. Field of the Invention
The present invention relates to a novel type of MOS-type semiconductor power component, this component being generally called a discrete component although several such components may be provided on the same chip, and/or they can be associated with logic circuits provided on the same chip.
2. Discussion of the Related Art
FIGS. 1A and 1B are a partial cross-section view and a top view of an example of the structure of a conventional multicellular vertical MOS power component.
This transistor is formed from a lightly-doped N-type layer or substrate 1 including, on its rear surface side, a heavily-doped N-type layer 2 (N+). Conversely to what is shown, the N+ layer may be much thicker than the N substrate. On the upper surface side of substrate 1 are formed P wells including a more heavily doped central portion 3 and a more lightly doped peripheral portion 4. Substantially at the center of the P wells is formed a heavily-doped N-type ring 5. Portion 6 of the P well external to N well 5 is topped with a conductive gate 7 insulated by a thin insulating layer 8. The upper surface and the lateral surface of gate 7 are insulated by an insulating layer 9 and the assembly is coated with a source metallization MS. The lower surface of the component is coated with a drain metallization MD. All the gates 7 are connected to a common gate terminal, not shown.
FIG. 1B is a top view of the structure without the gate and source metallization MS. The same elements are designated therein with the same references as in FIG. 1A.
For the simplicity of the drawing, each cell has been shown according to a square pattern. Other shapes are possible and currently used. When the source is negative with respect to the drain and the gate is properly biased, the current flows from the drain to the source, through the channel region in the direction of arrows 1 illustrated in FIGS. 1A and 1B in a portion of the structure. Similar currents flow from each of the cells. These currents essentially flow vertically, whereby the MOS transistor is said to be vertical.
A disadvantage of vertical MOS power transistors is their on-state resistance. Indeed, practical considerations make it difficult to optimize the thicknesses of the various layers and regions according to the desired transistor characteristics. In particular, the thickness of N-type layer 1 must be sufficiently high for the component to have a desired breakdown voltage but must also be as small as possible to limit the on-state resistance of the component. N+ layer 2 is used to take an ohmic drain contact on the rear surface. Its thickness could be reduced to a few micrometers, but this would lead to too thin silicon wafer thicknesses (<100 μm), incompatible with current production tools. Very thick N+ layers 2 (of a few hundreds of micrometers) are thus used. This layer then introduces an additional series resistance that reduces the on-state performances of the transistor.
Another disadvantage of vertical components is that the channel width (perimeter of P wells 4) depends in particular on the surface of the semiconductor chip taken up by the transistor and cannot be increased beyond certain limits.
A MOS transistor has been described, only as an example of a vertical MOS-type component. The problems indicated hereabove generally relate to MOS power or vertical high-power components, for example, insulated-gate bipolar transistors (IGBT) and other voltage-control enrichment or depletion components, of MOS or Schottky-MOS type.